Datacom Systems D56 Especificaciones Pagina 25
- Pagina / 108
- Tabla de contenidos
- MARCADORES
Valorado. / 5. Basado en revisión del cliente
Si5040
Rev. 1.3 25
5.8.1.1. Dynamic Register Control
The dynamic control of RxLoopFAcq (Register 98) is required to ensure the locking performance of the CDR. It is
required for all applications that RxLoopFAcq be set to 98h when RX LOL is asserted and to 00h when RX LOL is
deasserted. Only the default value and the value given above are supported for writes to Register 98. Any read
back of this register will not necessarily return the value written. If a valid reference clock is applied at pins 13,14
and rxRefclkEn = 1 (reg7[0]) and Rx VCOCAL = x0b (reg8[2:1]), then the dynamic register write to register 98 is
not necessary.
In addition, for proper LOL performance, RxPDGainAcq (Register 77) must be written once to 0Dh after power is
applied or a SW reset is implemented. If a valid reference clock is applied at pins 13,14 and rxRefclkEn = 1
(reg7[0]) and Rx VCOCAL = x0b (reg8[2:1]), then it is not necessary to write to register 77.
5.8.2. Frequency LOL
The Si5040 supports the use of a ~622 MHz or ~155 MHz (/64 or /16) reference clock. The reference clock
frequency is selected in the ChipConfig1 register (Register 2). There are two ways in which FREQLOL is selected.
When register7[3:2] = 10b, then FREQLOL is selected. When register7[3] = 0 and register7[1] = 1, then FREQLOL
is selected. LOL is asserted if the recovered clock frequency deviates from the reference clock frequency by
>±1000 ppm. LOL is de-asserted if the recovered clock is within ±200 ppm of the reference clock frequency. Refer
to Figure 14 for CDR and VCO behaviors upon declaring LOL.
5.8.3. Acquisition Time Enhancement
The acquisition lock time for a signal applied at RXDIN can be reduced to less than 15 ms by the following register
writes:
1. Write register 86 = 0011 1000 = 38h.
2. Write register 67 = 0100 0001 = 41h.
3. Write register 68 = 0000 0011 = 03h.
5.8.4. LOL Interrupt
LOL may be configured to generate an interrupt. The status of the LOL interrupt bit can be read from the
RxintStatus register (Register 5). The status of LOL may also be read from the RxAlarmStatus register (Register 9).
LOL may also be asserted upon activation of LOS (see "5.4. Receiver Loss of Signal Alarm (LOS)" on page 20 and
Figure 15 on page 26). Receive data (RD) may be squelched on LOL. This option is configured in the
RxdPathConfig register (Register 28).
- Features 1
- Applications 1
- Description 1
- Functional Block Diagram 1
- 2 Rev. 1.3 2
- TABLE OF CONTENTS 3
- Measurement 4
- 2. Electrical Specifications 5
- Table 2. DC Characteristics 6
- 8 Rev. 1.3 8
- = 1.8 V +5/–10%, T 8
- = –40 to 95 C) 8
- 10 Rev. 1.3 10
- Table 7. CMU Timing Modes 12
- Rev. 1.3 13 13
- Table 8. AC Characteristics—I 14
- C Bus Lines (SD, SCK) 14
- 765432 76543210 15
- Read Command Read Data 15
- 16 Rev. 1.3 16
- Rev. 1.3 17 17
- 4. Functional Description 18
- Normalized Output Amplitude 19
- 5.2. Limiting Amplifier 20
- Rev. 1.3 21 21
- 22 Rev. 1.3 22
- 5.5. Receiver Slice Control 23
- 5.7. Reference Clock 24
- Rev. 1.3 25 25
- 26 Rev. 1.3 26
- Rev. 1.3 27 27
- 5.9. Receiver Phase Adjust 28
- 6. Transmitter 29
- 30 Rev. 1.3 30
- Rev. 1.3 31 31
- 32 Rev. 1.3 32
- 7. Loopback Modes 33
- 8. Looptime Mode 33
- 10.1. I 35
- C Interface 35
- 10.2. SPI-Like Interface 36
- 11. Interrupt Functionality 37
- 38 Rev. 1.3 38
- Rev. 1.3 39 39
- 13. Si5040 Register Summary 40
- 44 Rev. 1.3 44
- 46 Rev. 1.3 46
- Rev. 1.3 47 47
- 48 Rev. 1.3 48
- Rev. 1.3 49 49
- 50 Rev. 1.3 50
- 52 Rev. 1.3 52
- Register 10 52
- Rev. 1.3 53 53
- 54 Rev. 1.3 54
- 56 Rev. 1.3 56
- 00 0000 0000 = 0 mV 56
- 11 1111 1111 = 1022 mV 56
- Rev. 1.3 57 57
- Rev. 1.3 59 59
- 60 Rev. 1.3 60
- Note: Default = 10 (decimal) 60
- Note: Default = 15 (decimal) 60
- Rev. 1.3 61 61
- Rev. 1.3 63 63
- Exponent 69
- 70 Rev. 1.3 70
- 72 Rev. 1.3 72
- Rev. 1.3 73 73
- 74 Rev. 1.3 74
- Rev. 1.3 75 75
- 76 Rev. 1.3 76
- Rev. 1.3 77 77
- 78 Rev. 1.3 78
- Rev. 1.3 79 79
- 80 Rev. 1.3 80
- Rev. 1.3 81 81
- 82 Rev. 1.3 82
- Rev. 1.3 83 83
- 84 Rev. 1.3 84
- Rev. 1.3 85 85
- 86 Rev. 1.3 86
- Note: Default = 1 (decimal) 86
- Note: Default = 8 (decimal) 86
- Rev. 1.3 87 87
- Bit D7 D6 D5 D4 D3 D2 D1 D0 87
- Rev. 1.3 89 89
- Rev. 1.3 95 95
- 96 Rev. 1.3 96
- 98 Rev. 1.3 98
- Rev. 1.3 99 99
- 14. Pin Descriptions: Si5040 100
- Rev. 1.3 101 101
- Input/Output 101
- 102 Rev. 1.3 102
- 15. Ordering Guide 103
- 16. Package Outline: Si5040 104
- Rev. 1.3 105 105
- DOCUMENT CHANGE LIST 106
- Revision 0.86 to Revision 1.2 107
- Revision 1.2 to Revision 1.3 107
- CONTACT INFORMATION 108
Relacionado con productos y manuales para Redes Datacom Systems D56
(44 paginas)© 2020, manymanuals.es. Todos los derechos reservados | 0.041 s |
Manymanuals.com
Manymanuals.de
Manymanuals.fr
Manymanuals.it
Manymanuals.pl
Manymanuals.cz
Manymanuals.es
Manymanuals-pt.com
Comentarios a estos manuales